--************************************************--
--**  Aritmeticko-logicka jednotka pro Hazard   **--
--**   Autor: Leos Marsalek    (c) 2002-2003    **--
--**     E-mail: Leos.Marsalek@tiscali.cz       **--
--**      Spolupracovali : Lukas Vaculík,       **--
--**              Miroslav Copian               **--
--************************************************--
library IEEE;                                                         -- Zpristupneni knihovny IEEE Std_logic
use IEEE.std_logic_1164.all;

entity ALU is                                                                   -- definice entity
    
port (SRC,DSTin STD_Logic_vector (15 downto 0);
          
resultout STD_Logic_vector (15 downto 0);
          
carryout STD_LogicCinin STD_logic;
          
codein STD_logic_vector(downto 0);
          
clk,enablein STD_logic);
          
end;
                                                                                
-- vlastní architektura
Architecture aritmetika of ALU is  
Signal 
vysledek
:STD_logic_vector (15 downto 0); 
procedure secti(a,b:STD_logic_vector;cin STD_logic;signal                     -- Procedura perfektne funguje
          
z:out  STD_logic_vector;signal Coutout STD_logic is
variable prenos:STD_Logic;
begin      
      
prenos
:=c;
      
for i in 0 to 15 loop 
          z
(i) <= (a(ixor b(i)) xor prenos;
          
prenos := (a(iand b(i)) or (prenos and a(i)) or (prenos and b(i));
      
end loop;
      
Cout<=prenos;
end;

Procedure Jmp(a,dstin STD_logic_vector;signal vysl:out std_logic_vector;      -- procedura k vypoctu skoku
          
cinstd_logicsignal CCout Std_Logicis
     
variable x:std_logic;
     
variable b:std_logic_vector(15 downto 0);
     
begin
          
x
:=a(5);
          
b:=a;
          
for i in 6 to 15 loop
               b
(i):=x;     
          
end loop;
          
secti(b,DST,cin,vysl,CC);
     
end

component registr16 is                                                        -- vyuziti registru
Port(Ain STD_LOGIC_vector (15 downto 0);bout STD_LOGIC_vector (15 downto 0);clk,Enable:in STD_LOGIC);
end component registr16;


begin                                                                           -- vlastni architektura
     
vypocetprocess (DST,Cin,SRC,Code,clk)
          
begin
               
case code is
                    
when "1111" => vysledek<=SRC;         -- mov
                    
when "0000" => vysledek<="0000000000000000";  --clear
                    
when "1110" =>  secti(SRC,DST,Cin,vysledek,Carry);          -- Add Pro alu A + B +Cin
                    
When "1100" =>  secti(SRC,not DST,Cin,vysledek,Carry);      -- Subb Pro alu A + not B + cin
                    
When "0111" =>  Jmp(SRC,dst,vysledek,'0',carry);  -- jmp instrukce
                    
When others=> Null;
               
end case;
          
end process;
 
Adr_reg:registr16 port map(Vysledek,result,clk,enable);            --D registr
end;